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? semiconductor components industries, llc, 2006 july, 2006 ? rev. 6 1 publication order number ncp1561/d ncp1561 push?pull pwm controller for 48 v telecom systems the ncp1561 push ? pull pwm controller contains all the features and flexibility needed to implement high efficiency dc ? dc converters using voltage or current ? mode control. this device can be configured in any dual ended topology such as push ? pull or half ? bridge. it can also be used for forward topologies requiring a 50% maximum duty cycle. this device is ideally suited for 48 v telecom, 42 v automotive systems and 12 v input applications. the ncp1561 cost effectively reduce system part count by incorporating a high voltage startup regulator, line undervoltage detector, single resistor oscillator setting, dual mode overcurrent protection, soft ? start and single resistor feedforward ramp generator. the oscillator frequency can be adjusted up to 250 khz. features ? internal high voltage startup regulator ? minimum operating voltage of 21.5 v ? voltage or current ? mode control capability ? single resistor oscillator frequency setting ? adjustable frequency up to 250 khz ? fast line feedforward ? line undervoltage lockout ? dual mode overcurrent protection ? programmable maximum duty cycle control ? maximum duty cycle proportional to line voltage ? programmable soft ? start ? precision 5.0 v reference ? pb ? free package is available* typical applications ? 48 v telecommunication power converters ? industrial power converters ? 42 v automotive systems *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. device package shipping ? ordering information ncp1561dr2 so ? 16 2500/tape & reel ncp1561 = device code a = assembly location wl = wafer lot y = year ww = work week g = pb ? free package marking diagram so ? 16 d suffix case 751b 1 1 awlywwg ncp1561 pin assignments v in v aux uv out1 ramp_out gnd ff out2 cs ramp_in cskip v ref r t v ea dc max ss ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. http://onsemi.com NCP1561DR2G so ? 16 (pb ? free) 2500/tape & reel
ncp1561 http://onsemi.com 2 figure 1. half ? bridge block diagram vin tx1 m1 lout cout ncp1561 + ? m2 opto error amplifier driver high side driver m3 out1 out1 out2 startup feedforward out2 m4 c1 c2 v in gnd uv cs ff high voltage startup regulator fault detection oscillator modulator figure 2. simplified block diagram thermal shutdown 5.0 v reference v aux ss v ea r t output stage out1 out2 uv dc max v ref cskip ramp_out ramp_in
ncp1561 http://onsemi.com 3 figure 3. ncp1561 block diagram v ea ? + ? + cs s r q reset dominant latch c ss 10 5 12 stop c cskip clock enable_ss 10.8 pf ff ramp (adjustable) * trimmed during manufacturing to obtain 1.3 v with r t = 101 k v in r ff ff 4 + current mirror ? + 2 v 10 pf i 1 + ? ? 2 v 7 oscillator ramp 2 v + ? 8 2 v max dc comparator pwm comparator + ? soft ? start comparator 1.0 v + ? 1.2 v + ? ss 9 one shot pulse ? + 6 ? + 2 v + ? 2 1.3 v* ramp_in v ref dc max + v dc(inv) ? r mdp r p c ff i ff disable + v ? ? + r t (600 ns) one shot pulse clock tf/f q out1 out2 15 13 3 ramp_out buffer v aux v aux cskip i 1 r t q 6.7 k 5.3 k v ref 12 a 2 k 20 k 29 k 29 k 38 k v ref i v 125 k + ? + ? 5.0 v reference v in 16 1 11 stop disable s r q dominant reset latch (250 ns) dis 2 uv one shot pulse + ? thermal shutdown ? + + ? 1.52 v + ? v aux c aux v in i aux v aux enable_ss v aux(on) v ref disable_v ref v aux(on) /v aux(off) output latch 6 a v ref r ea
ncp1561 http://onsemi.com 4 pin description pin name application information 1 v in this pin is connected to the bulk dc input voltage supply. a constant current source supplies current from this pin to the capacitor connected on the v aux pin. the charge current is typically 13.0 ma. input voltage range is 21.5 v to 150 v. 2 uv input supply voltage is scaled down and sampled by means of a resistor divider. the supply voltage must be scaled such that the voltage on the uv pin is 1.54 v at the minimum input voltage. 3 ramp_out internal feedforward (ff) ramp output. this signal can be externally routed to the ramp_in pin for voltage ? mode control operation. 4 ff an external resistor between v in and this pin adjusts the amplitude of the ff ramp inversely proportional to v in . by varying the feedforward ramp amplitude in proportion to the input voltage, changes in loop bandwidth resulting from v in changes are eliminated. 5 cs overcurrent sense input. if the cs voltage exceeds 0.95 v or 1.15 v, the converter enters the cycle by cycle or cycle skip current limit mode, respectively. 6 cskip the capacitor connected to this pin sets the cycle skip period. once a cycle skip fault is detected, the capacitor connected to this pin is discharged. the capacitor is then charged with a constant current of 12 a. the cycle skip period expires, once the voltage on this capacitor reaches 2.0 v. a soft ? start sequence follows at the conclusion of the fault period. 7 r t a single external resistor between this pin and gnd sets the fixed oscillator frequency. 8 dc max an external resistor between this pin and gnd sets the voltage on the max dc comparator inverting input. the duty cycle is limited by comparing the voltage on the max dc comparator inverting input to the feedforward ramp. 9 ss an internal 6.0 a current source charges the external capacitor connected to this pin. the duty cycle is limited during startup by comparing the voltage on this pin to the oscillator ramp. the soft ? start comparator limits the duty cycle while the ss voltage is below 2.0 v. 10 v ea the error signal from an external error amplifier is fed into this input and compared to the feedforward ramp. a series diode and resistor offset the voltage on this pin before it is applied to the pwm comparator inverting input. 11 v ref precision 5.0 v reference output. maximum output current is 6.0 ma. 12 ramp_in this pin configures the ncp1561 for voltage or current ? mode control. the internal feedforward ramp (voltage ? mode) or a signal proportional to the inductor current (current ? mode) is fed into this input and compared to the signal in the v ea pin. 13 out2 output 2. 14 gnd control circuit ground. 15 out1 output 1. 16 v aux positive input supply voltage. this pin is connected to an external capacitor for energy storage. an internal current source supplies current from v in to this pin. once the voltage on v aux reaches approximately 10.3 v, the current source turns off. it turns on again once v aux falls to 7 v. during normal operation, power is supplied to the ic via this pin, by means of an auxiliary winding. the startup circuit is disabled if the voltage on the v aux pin exceeds 10.3 v.
ncp1561 http://onsemi.com 5 maximum ratings rating symbol value unit input line voltage v in ? 0.3 to 150 v auxiliary supply voltage v aux ? 0.3 to 16 v auxiliary supply input current i aux 35 ma out1 and out2 voltage v out ? 0.3 to (v aux + 0.3 v) v out1 and out2 output current i out 10 ma 5.0 v reference voltage v ref ? 0.3 to 6.0 v 5.0 v reference output current i ref 6.0 ma all other inputs/outputs voltage v io ? 0.3 to v ref v all other inputs/outputs current i io 10 ma operating junction temperature t j ? 40 to 150 c storage temperature range t stg ? 55 to 150 c power dissipation at t a = 25 c p d 0.77 w thermal resistance, junction ? to ? ambient r ja 130 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. a. this device series contains esd protection and exceeds the following tests: pin 1: pin 1 is the hv startup of the device and is rated to the max rating of the part, or 150 v. machine model method 150 v. pins 2 ? 16: human body model 2000 v per mil ? std ? 883, method 3015. machine model method 200 v.
ncp1561 http://onsemi.com 6 electrical characteristics (v in = 48 v, v aux = 12 v, v ea = 2 v, r t = 101 k , c cskip = 6800 pf, r d = 60.4 k , r ff = 432 k , for typical values t j = 25 c, for min/max values, t j = ? 40 c to 125 c, unless otherwise noted) characteristic symbol min typ max unit startup control and v aux regulator v aux regulation startup threshold/v aux regulation peak (v aux increasing) minimum operating v aux valley voltage after turn ? on hysteresis v aux(on) v aux(off) v h 9.7 6.6 ? 10.3 7.0 3.3 10.8 7.4 ? v minimum startup voltage (pin 1) i start = 1.0 ma, i ref = 0 ma, v aux = v aux(on) ? 0.2 v v start(min) ? 18.3 21.5 v startup circuit output current v aux = 0 v t j = 25 c t j = ? 40 c to 125 c v aux = v aux(on) ? 0.2 v t j = 25 c t j = ? 40 c to 125 c i start 13 10 10 8.0 17 ? 13 ? 21 25 17 19 ma startup circuit off ? state leakage current (v in = 150 v) t j = 25 c t j = ? 40 c to 125 c i start(off) ? ? 23 ? 50 100 a startup circuit breakdown voltage (note 1) i start(off) = 50 a, t j = 25 c v br(ds) 150 ? ? v auxilliary supply current after v aux turn ? on outputs disabled v ea = 0 v v uv = 0 v outputs enabled i aux1 i aux2 i aux3 ? ? ? 3.3 1.8 4.1 5.0 2.5 6.5 ma line undervoltage detector undervoltage threshold (v in increasing) v uv 1.40 1.54 1.64 v undervoltage hysteresis v uv(h) 0.080 0.095 0.120 v undervoltage propagation delay to output t uv ? 250 ? ns current limit and thermal shutdown cycle by cycle threshold voltage i lim1 0.89 0.95 1.03 v propagation delay to output (v ea = 2.0 v) v cs = i lim1 to 2.0 v, measured when out1 reaches 10 v. t ilim ? 86 150 ns cycle skip threshold voltage i lim2 1.05 1.15 1.24 v cycle skip charge current (v cskip = 0 v) i cskip 8.0 12.3 15 a thermal shutdown threshold (junction temperature increasing, note 1) t shdn ? 180 ? c thermal shutdown hysteresis (junction temperature decreasing, note 1) t h ? 17 ? c 1. guaranteed by design only.
ncp1561 http://onsemi.com 7 electrical characteristics (v in = 48 v, v aux = 12 v, v ea = 2 v, r t = 101 k , c cskip = 6800 pf, r d = 60.4 k , r ff = 432 k , for typical values t j = 25 c, for min/max values, t j = ? 40 c to 125 c, unless otherwise noted) (continued) characteristic symbol min typ max unit control outputs frequency (r t = 101 k ) t j = 25 c t j = ? 40 c to 125 c f osc1 143 137 150 ? 157 163 khz frequency (r t = 59 k ) t j = 25 c t j = ? 40 c to 125 c f osc2 228 220 240 ? 252 260 khz output voltage (i out = 0 ma) low state high state v ol v oh ? ? 0.25 11.8 ? ? v drive resistance (v in = 15 v) sink (v ea = 0 v, v out = 2 v) source (v ea = 3 v, v out = 10 v) r snk r src 20 50 36 88 80 170 rise time (c l = 100 pf, 10% to 90% of v oh ) t on ? 32 ? ns fall time (c l = 100 pf, 90% to 10% of v oh ) t off ? 19 ? ns maximum duty cycle comparator maximum duty cycle (v in = 36 v) r p = 0 , r mdp = open r p = open, r mdp = open (note 2) dc max 34 48 38 ? 44 50 % open circuit voltage v dcmax 0.49 0.74 0.90 v soft ? start charge current (v ss = 1.0 v) i ss(c) 5.0 6.2 7.4 a discharge current (v ss = 5.0 v, v uv = 1.0 v) i ss(d) 20 50 ? ma pwm comparator input resistance (v 1 = 1.25 v, v 2 = 1.50 v) r in(vea) = (v 2 ? v 1 ) / (i 2 ? i 1 ) r in(vea) 8.0 22 60 k lower input threshold v ea(l) 0.7 0.92 1.1 v delay to output (from v oh to 0.5 v oh ) t pwm ? 200 ? ns 5.0 v reference output voltage (i ref = 0 ma) t j = 25 c t j = ? 40 c to 125 c v ref 4.9 4.8 4.96 ? 5.1 5.1 v load regulation (i ref = 0 to 6 ma) v ref(load) ? 10 50 mv line regulation (v aux = 7.5 v to 16 v) v ref(line) ? 50 100 mv 2. 50% maximum duty cycle guaranteed by design.
ncp1561 http://onsemi.com 8 typical characteristics figure 4. auxiliary supply voltage thresholds versus junction temperature figure 5. startup circuit output current versus junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 5 6 7 8 9 10 11 12 125 100 75 50 25 0 ? 25 ? 50 9 10 11 12 13 14 15 19 figure 6. startup circuit output current versus auxiliary supply voltage figure 7. startup circuit output current versus line voltage v aux , auxiliary supply voltage (v) v in , line voltage (v) 12 10 8 6 4 2 0 12.5 13.0 14.5 15.0 15.5 16.0 16.5 17.5 150 125 100 75 50 25 0 0 4 8 12 16 20 figure 8. startup circuit off ? state leakage current versus line voltage figure 9. auxiliary supply current versus junction temperature v in , line voltage (v) t j , junction temperature ( c) 150 125 100 75 50 25 0 0 5 10 15 20 25 30 40 125 100 75 50 25 0 ? 25 ? 50 4.5 0.5 1.0 1.5 2.0 2.5 3.5 4.0 v aux , auxiliary supply voltage (v) 150 150 16 17 18 i start , startup circuit output current (ma) 17.0 i start , startup circuit output current (ma) i start , startup circuit output current (ma) 35 i start(off) , startup circuit off ? state leakage current ( a) 150 3.0 i aux , auxiliary supply current (ma) startup threshold minimum operating threshold v aux = 0 v v aux = v aux(on) ? 0.2 v t j = ? 40 c t j = 25 c t j = 125 c t j = ? 40 c t j = 25 c t j = 125 c v ea = 0 v v uv = 0 v v aux = 12 v v in = 48 v v in = 48 v v aux = v aux(on) ? 0.2 v v aux = 12 v 14.0 13.5
ncp1561 http://onsemi.com 9 typical characteristics figure 10. operating auxiliary supply current versus junction temperature figure 11. line undervoltage threshold versus junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 125 100 75 50 25 0 ? 25 ? 50 1.30 1.35 1.40 1.45 1.50 1.70 figure 12. line undervoltage hysteresis versus junction temperature t j , junction temperature ( c) 150 125 100 25 0 ? 25 ? 50 70 80 90 100 110 120 140 figure 13. current limit thresholds versus junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0.90 0.95 1.00 1.05 1.10 1.15 1.25 1.30 i aux3 , operating auxiliary supply current (ma) 150 150 1.55 1.60 1.65 v uv , line undervoltage threshold (v) 130 v uv(h) , line undervoltage threshold hysteresis (mv) 150 1.20 i lim , current limit thresholds (v) 75 50 f osc = 250 khz cycle skip cycle by cycle v aux = 12 v dc 50% f osc = 150 khz f osc = 100 khz figure 14. current limit propagation delay versus junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 70 75 80 85 90 95 115 120 t ilim , current limit propagation delay (ns) 150 100 105 110 v aux = 12 v measured from v oh to 0.5 v oh figure 15. oscillator frequency versus junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 75 100 125 150 175 200 300 150 225 250 275 f osc , oscillator frequency (khz) r t = 148 k r t = 101 k r t = 50.6 k
ncp1561 http://onsemi.com 10 typical characteristics figure 16. oscillator frequency versus junction temperature figure 17. oscillator frequency versus timing resistor r t , timing resistor (k ) 400 300 250 200 150 100 50 0 50 100 150 200 300 250 f osc , oscillator frequency (khz) 350 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 142.5 145.0 147.5 150.0 152.5 155.0 150 157.5 f osc , oscillator frequency (khz) r t = 101 k t j = 25 c dc 50% t j , junction temperature ( c) 150 125 100 25 0 ? 25 ? 50 20 30 40 50 60 70 100 120 110 r snk/src outputs drive resistance ( ) 50 75 80 90 r src (v ea = 0 v, v out = 10 v) r snk (v ea = 3 v, v out = 2 v) v aux = 12 v figure 18. outputs drive resistance versus junction temperature figure 19. outputs rise time versus load capacitance c l , load capacitance (pf) 200 150 100 50 0 0 10 20 30 40 50 60 80 70 t on , outputs rise time (ns) t j = ? 40 c t j = 25 c t j = 125 c 175 125 75 25 measured from 10% to 90% of v oh v aux = 12 v figure 20. outputs fall time versus load capacitance c l , load capacitance (pf) 200 150 100 50 0 0 5 10 15 20 25 35 30 t off , outputs fall time (ns) t j = ? 40 c t j = 25 c t j = 125 c 175 125 75 25 measured from 90% to 10% of v oh v aux = 12 v figure 21. feedforward internal resistance versus junction temperature 15 0 125 100 75 0 ? 25 ? 50 9 10 11 12 13 14 15 19 17 feedforward internal resistance (k ) 50 25 16 18 t j , junction temperature ( c)
ncp1561 http://onsemi.com 11 typical characteristics t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 3.0 3.5 4.0 4.5 5.0 5.5 6.5 7.0 150 6.0 i ss(c) , soft ? start charge current ( a) 30 35 40 45 50 55 65 70 60 charge discharge 525 450 225 150 75 0 0 5 10 20 30 45 dc max , maximum duty cycle (%) 375 300 15 25 t j = ? 40 c t j = 125 c 40 35 v ea = 3.0 v dc max pin = open t j , junction temperature ( c) 15 0 125 100 75 0 ? 25 ? 50 20 25 35 40 45 50 dc max , maximum duty cycle (%) 50 25 r p = open, r mdp = open r p = 0 , r mdp = open v in = 36 v r ff = 432 k figure 22. maximum duty cycle versus feedforward current figure 23. maximum duty cycle versus junction temperature figure 24. soft ? start charge/discharge currents versus junction temperature i ss(d) , soft ? start discharge current (ma) i ff , feedforward current ( a) 50 30 figure 25. v ea input resistance versus junction temperature t j , junction temperature ( c) 150 100 50 0 ? 50 0 10 20 40 50 30 r in(vea) , v ea input resistance (k ) ? 25 125 75 25 t j , junction temperature ( c) 150 125 100 25 0 ? 25 ? 50 0.75 0.80 0.85 0.95 1.00 v ea(l) , pwm comparator lower input threshold (v) 50 75 0.90 figure 26. pwm comparator lower input threshold versus junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 4.91 4.93 4.95 4.97 5.01 15 0 v ref , reference voltage (v) i ref = 0 ma i ref = 6 ma 4.99 figure 27. reference voltage versus junction temperature r ff = 432 k v in = 48 v
ncp1561 http://onsemi.com 12 detailed operating description the ncp1561 is a push ? pull pwm controller for use in 48 v telecom power converters or 42 v automotive systems. this controller contains all the features and flexibility required in high density isolated dc ? dc modules and on ? board designs for telecom and automotive systems. it can be configured for operation in voltage ? mode with feedforward or current ? mode control. the extensive set of features included in the ncp1561 facilitates system design and reduces overall system cost and component count by incorporating supervisory functions and components traditionally found outside the controller. features of the ncp1561 include a high voltage startup regulator, fast line feedforward, a line undervoltage lockout, dual mode overcurrent protection, programmable maximum duty cycle limit, programmable soft ? start and external voltage reference. voltage ? mode operation with line feedforward provides better line regulation without some of the traditional problems associated with current ? mode control. the controller is configured for voltage ? mode operation by routing the internal feedforward ramp output (ramp_out) to the pwm comparator non ? inverting input (ramp_in). the amplitude of the feedforward ramp varies inversely proportional to the input voltage. operation in current ? mode control is obtained by routing a signal proportional to the inductor current into the pwm comparator non ? inverting input (v ea pin). in either mode, the maximum duty cycle is inversely proportional to the line voltage, as configured by the dc max pin and ff pins. high voltage startup regulator the ncp1561 contains an internal high voltage startup regulator that eliminates the need for external startup components. in addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. the startup regulator consists of a constant current source that supplies current from the input line voltage (v in ) to the capacitor on the v aux pin (c aux ). the startup current is typically 13.0 ma. once v aux reaches approximately 10.3 v, the startup regulator turns off and the outputs are enabled. when v aux reaches 7.0 v, the outputs are disabled and the startup regulator turns on. this mode of operation is known as dynamic self supply (dss). the startup circuit sources current out of the v aux pin. it is recommended to place a diode between c aux and the auxiliary supply as shown in figure 28. this will allow the ncp1561 to charge c aux while preventing the startup regulator from sourcing current into the auxiliary supply. figure 28. recommended v aux configuration i start disable c aux i supply v aux i aux to auxiliary supply v in i start power to the controller while operating in the self ? bias or dss mode is provided by c aux . therefore, c aux must be sized such that a v aux voltage greater than 7.0 v is maintained while the outputs are enabled and the converter reaches regulation. also, the v aux discharge time (from 10.3 v to 7.0 v) must be greater than the soft ? start charge period to assure the converter turns on. the startup circuit is rated at a maximum voltage of 150 v. if the device operates in the dss mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. the startup regulator is disabled by biasing v aux above 7.0 v once the outputs are enabled. it can also be disabled by biasing v aux above v aux(on) (typically 10.3 v). this feature allows the ncp1561 to operate from an independent 12 v ( 10%) supply. the independent supply should keep v aux above v aux(on) . otherwise the output latch will not be set and the outputs will remain off after a fault condition is cleared. if operating from an independent supply, the v in and v aux pins should be connected together.
ncp1561 http://onsemi.com 13 line undervoltage shutdown the ncp1561 incorporates a line undervoltage shutdown (uv) circuit. the undervoltage threshold is approximately 1.54 v. the uv circuit can be biased using an external resistor divider from the input line. the resistor divider must be sized to enable the controller once v in is within the required operating range. once the uv condition is removed and v aux reaches v aux(on) , the controller initiates a soft ? start cycle, as shown in figure 29. the uv pin can also be used to implement a remote enable/disable function. biasing the uv pin below its uv threshold disables the converter. figure 29. soft ? start timing diagram (using auxiliary winding) 0 v 0 v 2 v 0 v 0 v 0 v out2 out1 soft ? start voltage uv voltage soft ? start 2 v v aux(off) v aux v aux(on) if the uv threshold is reached, once in normal operation, the soft ? start capacitor is discharged, and the outputs are immediately disabled as shown in figure 30. also, if an uv condition is detected, the 5.0 v reference supply is disabled. figure 30. uv fault timing diagram out2 out1 0 v 0 v 0 v uv voltage 0 v uv fault v aux(on) v aux(off) v aux v uv propagation delay to outputs (t uv )
ncp1561 http://onsemi.com 14 feedforward ramp generator the ncp1561 incorporates line feedforward (ff) to compensate for changes in line voltage. a ff ramp proportional to v in is generated and compared to the error signal. if the line voltage changes, the ff ramp slope changes accordingly. the duty cycle will be adjusted immediately instead of waiting for the line voltage change to propagate around the system and be reflected back on v ea . a resistor between v in and the ff pin (r ff ) sets the feedforward current (i ff ). the ff ramp is generated by charging an internal 10.8 pf capacitor (c ff ) with a constant current proportional to i ff . the ff ramp is finished (capacitor is discharged) once the oscillator ramp reaches 2.0 v. please refer to figure 3 for a functional drawing of the feedforward ramp generator. i ff is usually a few hundred microamps, depending on the operating frequency and the required duty cycle. if the operating frequency and maximum duty cycle are known, i ff is calculated using the equation below: i ff c ff v dc(inv) 125 k 6.7 k t on(max) where v dc(inv) is the voltage on the inverting input of the max dc comparator and t on(max) is the maximum on time. figure 22 shows the relationship between i ff and dc max . for example, if a system is designed to operate at an oscillator frequency of 150 khz, with a 45% maximum duty cycle at 36 v, the dc max pin can be grounded and i ff is calculated as follows: t 1 f 1 150 khz 6.66 s t on(max) dc max t 0.45 6.66 s 3.0 s i ff c ff v dc(inv) 125 k 6.7 k t on(max) 10.8 pf 1.0 v 125 k 6.7 k 3.0 s 67.2 a as the minimum line voltage is 36 v, the required feedforward resistor is calculated using the equation below: r ff v in i ff 12.0 k 36 v 67.2 a 12.0 k 523 k from the above calculations it can be observed that i ff is controlled predominantly by the value of r ff , as the resistance seen into the ff pin is only 12 k . if a tight maximum duty cycle control over temperature is required, r ff should have a low thermal coefficient. if current ? mode control is used and the ff ramp generator is not used for maximum duty cycle control, the ff ramp generator can be disabled grounding the ff pin.
ncp1561 http://onsemi.com 15 current limit the ncp1561 has two overcurrent protection modes, cycle by cycle and cycle skip. it allows the ncp1561 to handle momentary and hard shorts differently for the best tradeoff in system performance and safety. the outputs are disabled typically 86 ns after a current limit fault is detected. the cycle by cycle mode terminates the conduction cycle (reducing the duty cycle) if the voltage on the cs pin exceeds 0.95 v. the cycle skip mode is enabled if the voltage on the cs pin reaches 1.15 v. once a cycle skip fault is detected, the outputs are disabled, the soft ? start and cycle skip capacitors are discharged, and the cycle skip period (t cskip ) commences. the cycle skip period is set by an external capacitor (c cskip ). once a cycle skip fault is detected, the cycle skip capacitor is discharged followed by a charge cycle. the charge current is 12.3 a. the cycle skip period ends when the voltage on the cycle skip capacitor reaches 2.0 v. if the cycle skip period is known, the cycle skip capacitor is calculated using the equation below: c cskip t cskip 12.3 a 2v using the above equation, a cycle skip period of 11.0 s requires a cycle skip capacitor of 68 pf. the differences between the cycle by cycle and cycle skip modes are shown in figure 31. figure 31. overcurrent faults timing diagram cycle skip voltage 0 v 0 v 0 v 0 v 0 v out1 out2 cs voltage normal operation reset faults i lim1 i lim2 t cskip i lim v aux(off) v aux v aux(on) 2 v soft ? start once the cycle skip period is complete and v aux reaches v aux(on) , a soft ? start sequence commences. the possible minimum off time is set by c cskip . the actual off time is generally greater than the cycle skip period if operating in dss because it is the cycle skip period added to the time it takes v aux to cycle between v aux(off) and v aux(on) . if operating from an independent supply, the off time is the cycle skip period. oscillator the ncp1561 oscillator frequency is set by a single external resistor connected between the r t pin and gnd. the oscillator is designed to operate up to 250 khz. the voltage on the r t pin is laser trim adjusted during manufacturing to 1.3 v for an r t of 101 k . a current set by r t generates an oscillator ramp by charging an internal 10 pf capacitor as shown in figure 3. the period ends (capacitor is discharged) once the oscillator ramp reaches 2.0 v. if r t increases, the current and the oscillator ramp slope decrease, thus reducing the frequency. if r t decreases, the opposite effect is obtained. figure 17 shows the relationship between r t and the oscillator frequency.
ncp1561 http://onsemi.com 16 maximum duty cycle a dedicated internal comparator limits the maximum on time by comparing the ff ramp to v dc(inv) as shown in figure 3. if the ff ramp voltage exceeds v dc(inv) , the output of the max dc comparator goes high. this will reset the output latch, thus turning off the outputs and limiting the duty cycle. duty cycle is defined as: dc t on t t on f therefore, the maximum on time can be set to yield the desired dc if the operating frequency is known. the maximum on time is set by adjusting the ff ramp to reach v dc(inv) in a time equal to t on(max) as shown in figure 32. the maximum on time should be set for the minimum line voltage. as line voltage increases, the slope of the ff ramp increases. this reduces the duty cycle below dc max , which is a desirable feature as the duty cycle is inversely proportional to line voltage. figure 32. maximum on time limit waveforms oscillator ramp 0 v 0 v ff ramp t t on(max) v dc(inv) 2 v an internal resistor divider from a 2.0 v reference is used to set v dc(inv) . if the dc max pin is grounded, v dc(inv) is 1.0 v. if the pin is floating, v dc(inv) is 1.4 v. this is equivalent to 71% (36% dc) or 100% (50% dc) of a ff ramp, with a peak voltage of 1.4 v. v dc(inv) can be adjusted to other values by placing an external resistor network on the dc max pin. for example, if the minimum line voltage is 36 v, r ff is 432 k , oscillator frequency is 150 khz and a maximum duty cycle of 45% is required, v dc(inv) is calculated as follows: v dc(inv) i ff 6.7 k t on(max) c ff 125 k v dc(inv) 81.0 a 6.7 k 3.0 s 10.8 pf 125 k 1.2 v this can be achieved by connecting a 23.44 k resistor from the dc max pin to gnd. the maximum duty cycle limit can be disabled connecting a 100 k resistor between the dc max and v ref pins. 5.0 v reference the ncp1561 includes a precision 5.0 v reference output. the reference output is biased directly from v aux and it can supply up to 6 ma. load regulation is 50 mv and line regulation is 100 mv within the specified operating range. it is recommended to bypass the reference output with a 0.1 f ceramic capacitor. the reference output is disabled when an uv fault is present. pwm comparator in steady state operation, the pwm comparator adjusts the duty cycle by comparing the error signal to the ff ramp (voltage ? mode) or a ramp proportional to the inductor current (current ? mode). the error signal is fed into the v ea input. the ff ramp or the inductor ramp is fed into the ramp_in pin. if operating in voltage ? mode, the connection between the ramp_out and ramp_in pins should be as close as possible to minimize parasitic inductance. it can be easily routed underneath the package. the v ea input can be driven directly with an optocoupler and a pull up resistor (r ea ) from v ref as shown in figure 33. the drive of the control pin is simplified by internally incorporating a series diode and resistor. the series diode provides a 0.7 v of fset between the v ea input and the pwm comparator inverting input. the outputs are enabled if the v ea voltage is approximately 0.7 v above the valley voltage of the ramp (v valley ) in the ramp_in pin. figure 33. optocoupler driving v ea input ? + ? + pwm comparator ff ramp or inductor ramp feedback signal ramp_in r ea v ref v ea v ea v peak v valley 20 k 2 k 0 v 12 11 10 the pullup resistor is selected such that in the absence of the error signal, the voltage on the v ea pin exceeds the peak amplitude of the ramp in the ramp_in pin. otherwise, the converter may not be able to reach maximum duty cycle. if operating in voltage ? mode, r ea is calculated using the equation below: r ea 22 k v ref 0.7 v v valley 0.0515 i ff c ff f 1 where, c ff is the internal ff capacitor, typically 10.8 pf.
ncp1561 http://onsemi.com 17 soft ? start soft ? start (ss) allows the converter to gradually reach steady state operation, thus reducing startup stress and surges on the system. the duty cycle is limited during a soft ? start sequence by comparing the oscillator ramp to the ss voltage (v ss ) by means of the soft ? start comparator. once faults are removed and v aux reaches v aux(on) , a 6.2 a current sou rce starts to charge the capacitor on the ss pin. the soft ? start comparator controls the duty cycle while the ss voltage is below 2.0 v. once v ss reaches 2.0 v, it exceeds the oscillator ramp voltage and the soft ? start comparator does not limit the duty cycle. figure 34 shows the relationship between the outputs duty cycle and the soft ? start voltage. figure 34. soft start timing diagram out2 out1 v ss oscillator ramp if the soft start period is too long, v aux may discharge to 7 v before the converter output is completely in regulation causing the outputs to be disabled. if the converter output is not completely discharged when the outputs are re ? enabled, the converter will eventually reach regulation exhibiting a non ? monotonic startup behavior. but, if the converter output is completely discharged when the outputs are re ? enabled, the cycle may repeat and the converter will not start. in the event of an uv or cycle skip fault, the soft ? start capacitor is discharged. once the fault is removed, a soft ? start cycle commences. the soft ? start steady state voltage is approximately 4.1 v. control outputs the ncp1561 has two off ? phase control outputs, out1 and out2. figure 35 shows the relationship between out1 and out2. figure 35. control outputs timing diagram out1 out2 once v aux reaches v aux(on) , the internal startup circuit is disabled and the one shot pulse generator is enabled. if no faults are present, the outputs turn on. otherwise, the outputs remain off until the fault is removed and v aux reaches v aux(on) again. the control outputs are biased from v aux . the outputs can supply up to 10 ma each and their high state voltage is usually 0.2 v below v aux . therefore, the auxiliary supply voltage should not exceed the maximum input voltage of the driver stage. if the control outputs need to drive a lar ge capacitive load, a driver should be used between the ncp1561 and the load. figures 19 and 20 show the relationship between the output?s rise and fall times vs capacitive load. thermal protection internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. when activated, typically at 180 c, the controller is forced into a low power reset state, discharging the soft ? start capacitor and disabling the output drivers and the bias regulator. once the junction temperature falls below 163 c, the ncp1561 enters a soft ? start mode and it is allowed to resume normal operation. this feature is provided to prevent catastrophic failures from accidental device overheating. application information a dc ? dc converter for a 48 v telecom system is designed and implemented using the ncp1561. the converter delivers 125 w at 2.5 v and achieves a full load efficiency of 85%. the system is built using a 4 layer fr4, single sided board. the converter footprint is 3.25 in x 3.75 in. the components location within the board is shown in figure 36 and the complete circuit schematic is shown in figure 37. the bill of material is listed in table 1. the layout files are available. please contact your sales representative for more information.
ncp1561 http://onsemi.com 18 figure 36. demo board top view 3.75? 3.25?
ncp1561 http://onsemi.com 19 figure 37. ncp1561 demo board circuit schematic on/off 5v ref 5v ref outb outb sec_pwr vaux sec_pwr r36 0 c14 cr12 bav70 c31 0.1 c37 r27 10k u4 8 2 3 1 4 5 6 7 n/c in_a gnd n/c_1 in_b out_b vcc out_a r31 6.2 r34 c33 c22 100p cr4 bav70 cr1 bav70 c35 tx4 pulse_p0544 c6 0.01 c28 47 tx3 pulse_p0544 r33 r29 5.49k cr16 r1 1m r6 cr9 u6a lm258 + ? c25 r9 c36 cr11 c27 47 c9 r35 0 c38 q3 sud40n10 ? 25 x7 r25 + c29 r32 c15 e1 c7 22 c8 0.1 r2 c32 c5 0.1 u1 ncp1561 4 1 3 2 16 15 13 10 8 9 7 5 11 12 6 14 vff vin ramp_out uv vaux out1 out2 vea dcmax ss rt cs vref ramp_in c_skip gnd l1 r23 1.43k cr8 r37 0 c16 0.1 r28 21.0k q1 c2 10 c4 10 u7 tvl431a u3 8 2 3 1 4 5 6 7 n/c in_a gnd n/c_1 in_b out_b vcc out_a sfh615a ? 4 u8 c12 e2 lm2931 u2 8 3 4 1 7 6 2 5 vin gnd adj vout gnd gnd gnd sd r24 t1 pulse_ps8202t cr10 r8 24.9k r5 open c19 0.1 c40 open cr3 q5 cr6 r13 c1 10 l2 r4 r21 r17 29.4k cr18 e3 r16 1.0k q6 sud40n10 ? 25 e5 x6 c20 0.1 c17 0.1 q2 c10 0.12 x5 r3 cr19 open cr2 c24 0.1 c3 10 c21 cr14 cr17 u6b lm258 ? r18 6.2 r30 r26 c39 r19 6.2 e4 r7 open c13 0.1 c11 0.22 r20 r11 6.98 r12 4t 1t tx1 payton_9557 cr13 bav70 cr15 r22 10.0 tx5 pulse_p0544 r15 1.0k c23 0.1 q4 r14 r10 + c30 bav70 mmbt2907 10k 110n02 110n02 1000p 1.0 h 330 330 bav70 1000p 110n02 110n02 bav70 mmbt2907 10k vaux 249k 10k 100 1000p bav70 bav70 bav70 100 523k 46.4k vaux 124k bav70 bav70 bav70 750 47p bav70 bav70 bav70 vaux 1000p 100p 47p 750 10k 6.04k 10k mmbt2907 1000p 19.6 k 2700p 20.5k 1800p 100p 680p 21.0k + c26 1000p c34 c18 0.1 2.2 h 3t 1t open 2.5 v ? + + 36 ? 72 v ? mc33152 mc33152 0.1 0.1
ncp1561 http://onsemi.com 20 table 1. ncp1561 demo board bill of material quantity part reference part value vendor comments 4 c1 ? c4 c5750x7r1h106m 10 f tdk 50 v 13 c5, c8, c13 ? c20, c23, c24, c31 c3216x7r2a104k 0.1 f tdk 100 v 1 c6 c2012x7r1h103k 0.01 f tdk 50 v 1 c7 c4532x7r1c226mt 22 f tdk 16 v 5 c9, c12, c25, c26, c35 vj0805a102kxbat 1000 pf vishay (vitramon) 100 v 1 c10 vj1206y124kxxat 0.12 f vishay (vitramon) 25 v 1 c11 c3216x7r1h224kt 0.22 f tdk 25 v 3 c21, c22, c34 vj0805a101kxbat 100 pf vishay (vitramon) 100 v 2 c27, c28 c4532x5r0j476m 47 f tdk 6.3 v 2 c29, c30 t495x337k006as 330 f kemet 6 v 1 c32 vj0805a681kxbat 680 pf vishay (vitramon) 100 v 1 c33 vj1206a182kxbat 1800 pf vishay (vitramon) 100 v 1 c36 vj1206a102kxbat 1000 pf vishay (vitramon) 100 v 2 c37, c38 vj0805a470kxbat 47 pf vishay (vitramon) 100 v 1 c39 vj1206a272kxbat 2700 pf vishay (vitramon) 100 v 1 c40 ? open ? open 16 cr1 ? cr4, cr6, cr8 ? cr18 bav70lt1 ? on semiconductor dual diode 1 cr19 ? open ? open 1 l1 do3316p ? 222 2.2 h coilcraft 1 l2 9558 1.0 h payton 4 q1, q2, q4, q5 ntd110n02r ? on semiconductor 24 v, n ? mosfet 2 q3, q6 sud40n10 ? 25 ? vishay 100 v, n ? mosfet 1 r1 crcw12061004fre4 1m vishay (dale) 1% 2 r2, r10 crcw1206101jrt1 100 vishay (dale) 5% 1 r3 crcw12065233frt1 523k vishay (dale) 1% 1 r4 crcw12064642frt1 46.4k vishay (dale) 1% 3 r5, r7, r34 ? open ? open 1 r6 crcw12061243frt1 124k vishay (dale) 1% 1 r9 crcw12062493frt1 249k vishay (dale) 1% 5 r12, r13, r14, r20, r21 crcw1206103jrt1 10k vishay (dale) 5% 1 r8 crcw12062492frt1 24.9k vishay (dale) 1% 1 r11 crcw12066r98frt1 6.98 vishay (dale) 1% 2 r15, r16 crcw12061001frt1 1.0k vishay (dale) 1% 1 r17 crcw12062942frt1 29.4k vishay (dale) 1% 3 r18, r19, r31 crcw25126r19frt1 6.2 vishay (dale) 5% 1 r22 crcw080510r0frt1 10 vishay (dale) 1% 1 r23 crcw12061431frt1 1.43k vishay (dale) 1% 1 r24 crcw12062052frt1 20.5k vishay (dale) 1% 1 r25 crcw12061962frt1 19.6k vishay (dale) 1% 2 r26, r28 crcw12062102frt1 21.0k vishay (dale) 1% 1 r27 crcw1206103jrt1 10k vishay (dale) 5% 1 r29 crcw12065491frt1 5.49k vishay (dale) 1% 1 r30 crcw12066041frt1 6.04k vishay (dale) 1% r32, r33 crcw12067500frt1 750 vishay (dale) 1% 3 r35 ? r37 crcw0603000zt 0 vishay (dale) 5% 1 t1 ps8202t ? pulse current sense transformer 1 tx1 9557 ? payton power transformer 3 tx3 ? tx5 p0544 ? pulse gate drive transformer 1 u1 ncp1561dr2 ? on semiconductor controller 1 u2 lm2931cd ? on semiconductor voltage regulator 2 u3, u4 mc33152d ? on semiconductor mosfet driver 1 u6 lm258d ? on semiconductor dual opamp 1 u7 tvl431asnt1 ? on semiconductor regulator 1 u8 sfh6156 ? 4 ? vishay poptocoupler 3 x5 ? x7 mmbt2907awt1 ? on semiconductor pnp transistor
ncp1561 http://onsemi.com 21 package dimensions so ? 16 d suffix case 751b ? 05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1561/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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